1. Field of the Invention
This invention relates to clock generation circuits and, more particularly, to delay locked loop circuits.
2. Description of the Related Art
Many circuits employ clock circuits that generate one or more clock signals having different frequencies from a reference clock. For example, a system may include reference clock generator or oscillator circuit that provides an output signal at a given frequency. The output signal may be used as a reference to generate any number of other clock signals for use in different parts of the system.
To generate the other clock signals with different frequencies, a frequency synthesizer such as a delay locked loop circuit, for example, may be used. More particularly, delay locked loop circuits are commonly used as clock multipliers capable of generating clocks having frequencies that are multiples of the reference clock frequency. However depending on the application, conventional phase/frequency detection circuits may sometimes exhibit false lock conditions during which the delay locked loop circuit may lock onto an incorrect edge of the feedback clock. As a result, the output signal may be incorrect.